(1) FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuits, and more particularly to a method for making more reliable bonding pads using a capping layer. This method eliminates the overetching of the bonding pads when the bonding pad openings are etched, while concurrently etching deeper fuse openings in the underlying insulating layers to the polysilicon fuse near the substrate surface.
(2) DESCRIPTION OF THE PRIOR ART
The reduction of the feature sizes of semiconductor devices using advanced semiconductor techniques, such as high-resolution lithography and directional etching, have dramatically increased the device packing density on integrated circuit chips formed on the substrate. However, as the device packing density increases, it is necessary to increase the number of electrical metal interconnect layers on the chip to effectively wire up the discrete devices on the substrate while reducing the chip size. For example, it is not uncommon to use between two and six levels of metal interconnect layers. Typically after completing the multilevel interconnect structure, bonding pads are formed on the top surface of the interconnect structure to provide external electrical connections to the chip. A passivation layer is then applied, such as a phosphorous doped glass, a silicon nitride, a silicon oxynitride layer, or a combination of these layers to passivate the chip from moisture and contamination.
Another concern as the density of the semiconductor devices increases on the chip is that the final product yield for many integrated circuits (chip yield) can dramatically decrease. For example, one circuit device that can experience this yield loss with increased device density is the dynamic random access memory (DRAM) currently having 64 megabits of memory on a chip. After the year 2000 the number of memory cells is expected to increase further to about 1 to 4 gigabits, and high final product yield will be difficult to achieve without utilizing cell redundancy and repair yield methods. One method of overcoming this lower yield on RAM devices is to provide additional rows of memory cells and fusing each row of cells. A laser is then used to open connections (fuses) in the patterned polysilicon layers on the substrate that are used to form the DRAM or SRAM devices. By this means defective rows of memory cells can be disabled and the address decoder circuits can be modified so that spare rows of memory cells are selected instead. To achieve this laser deletion, it is necessary to etch deep openings through the multilevels of insulating layers in the multilevel metal interconnect structure over the fuse portions of the patterned polysilicon layer. It is also common practice in the semiconductor industry to etch the bonding pad openings and the fuse openings using the same masking step to reduce manufacturing cost. Unfortunately, when the fuse openings are etched in the thick multilevels of insulation, the bonding pad openings can be overetched, essentially eroding away a major portion of the bonding pad causing reliability concerns.
To better appreciate this overetch problem, FIGS. 1-3 depict the problem of the prior art and are briefly described. The drawing in FIG. 1 is a schematic cross-sectional view showing a portion of a substrate 10 having an integrated circuit completed up to and including the bonding pad layer. The semiconductor devices formed on the substrate typically include patterned polysilicon layers that also serve as local interconnections which include portions for fuses 14, as shown in FIG. 1. For example, the polysilicon layer can be used to form the gate electrodes for field effect transistors (FETs) or bit lines on DRAM devices. A multilevel interconnect structure 16 is then formed over the devices to complete the electrical interconnections on the chip. Typically the interconnect structure 16 is composed of several layers of patterned metal, such as aluminum/copper (AlCu), with alternating insulating layers, such as silicon oxide (SiO.sub.2) or low dielectric insulators. Metal plugs are formed in the insulating layers as electrical interconnects between metal layers. The details of the interconnect structure 16 are not essential to understanding the problem and are therefore not depicted in detail in the Figs. to simplify the drawings and the discussion. As shown in FIG. 1, the bonding pad layer 18 is typically formed by depositing a multilayer conducting layer such as titanium nitride-AlCu-titanium nitride layers to a thickness of 9000 Angstroms. Bonding pads 18' are then formed by using a patterned photoresist etch mask 20 and conventional plasma etching to pattern the bonding pad layer 18, as shown in FIGS. 1 and 2. The bonding pads 18' are typically used to make external electrical connections to the chip for the I/O signals (input/output signals) and to provide power for the chip. FIG. 2 shows one of the bonding pads 18' making contact to one of the metal plugs 22 in the multilevel interconnect structure 16 as part of the electrical interconnections. Still referring to FIG. 2, a passivation layer 26 is deposited over the substrate to prevent moisture and contamination of the integrated circuits. Typically the passivation layer is composed of a doped glassy a silicon nitride, silicon oxynitride, or a combination of these insulating materials to prevent moisture and/or ion contamination from corroding and electrically degrading the semiconductor devices, respectively.
Still referring to FIG. 2 and more specifically to the nature of the problem, a photoresist layer 28 is patterned to form an etch mask for etching openings 1 in the passivation layer 26 to the bonding pads 18' while concurrently openings 2 are etched in the passivation layer and in the underlying insulating layers of the multilevel interconnect structure over the fuses 14, as shown in FIG. 3. However, because of the excessive etching in the relatively thick insulating layers, about 55,000 Angstroms, it is difficult to etch the fuse openings 2 to within the required depth D of 5000+/-3000 Angstroms without overetching the bonding pads 18' in the openings 1. As shown in FIG. 3, this overetching of the bonding pads results in a thinning of the bonding pads to a thickness E that is less than 4000 Angstroms, which causes reliability problems. The current etching conditions do not provide sufficient etch selectivity between the passivation layer and the bonding pads to prevent this overetching. For example, the current etching gases, such as CF.sub.4)/CHF.sub.3 /Ar, and etching parameters, such as at about 1100 Watts of power, can result in AlCu etch rates of 300 to 400 Angstroms per minute.
One method of forming bonding pads is described by Bryant et al., U.S. Pat. No. 5,403,777, in which bonding pads are formed in the shape of grid, and a second conducting layer is deposited to prevent pad lift-off. Another method for making low-resistance bond-pad interconnects is described by Doan et al., U.S. Pat. No. 5,384,284. The method uses an intermediate conducting layer to prevent Al.sub.2 O.sub.3 from forming on the Al bond pads, thereby preventing high resistance. In U.S. Pat. No. 5,290,588 by Romero et al., a method is described for eliminating "purple plague" which is an undesirable reaction of the gold (Au) layer on Al bonding pads. The method utilizes a TiW layer between the Al and the Au and an inert atmosphere anneal to form stable TiAl.sub.3 phase that prevents inter-diffusion between the Al and the Au. Liu et al. in U.S. Pat. No. 5,705,428 describe a method for preventing Ti lifting during and after metal etching by adding nitrogen during plasma etching, or during photoresist plasma strip, using an oxygen stream ambient. However, none of these references addresses the overetch bonding-pad problem described.
There is still a strong need in the semiconductor industry to provide a method for etching openings in a passivation layer to bonding pads and concurrently etching openings to the fuses without overetching the bonding pads.